HV2901 doc.# dsfp-HV2901 b011713 features ? 32-channel high voltage analog switch ? integrated bleed resistors on the outputs ? 2:1 multiplexer / demultiplexer ? 3.3v or 5.0v cmos input logic level ? 20mhz data shift clock frequency ? hvcmos technology for high performance ? very low quiescent power dissipation -10a ? low parasitic capacitance ? dc to 50mhz analog signal frequency ? -60db typical off-isolation at 5.0mhz ? cmos logic circuitry for low power ? excellent noise immunity ? cascadable serial data register with latches ? flexible operating supply voltages applications ? medical ultrasound imaging ? ndt metal faw detection ? piezoelectric transducer drivers ? inkjet printer heads ? optical mems modules general description the supertex HV2901 is a low charge injection 32-channel high voltage analog switch integrated circuit (ic) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. input data are shifted into a 32-bit shift registers that can then be retained in a 32-bit latch. to reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. data are clocked in during the rising edge of the clock. using hvcmos technology, this device combines high voltage bilateral dmos switches and low power cmos logic to provide effcient control of high voltage analog signals. the device is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +40v/-160v, +100v/-100v, and +160v/-40v. block diagram low charge injection 32-channel high voltage analog switch with bleed resistors rg nd level shifters vp p vnn latches cl r le 32-b it shift register cl k di n gn d vd d output switches do ut sw 0 sw 1 y0 1 sw 2 sw 3 y23 sw 28 sw 29 y2 82 9 sw 30 sw 31 y3 031 d le clr d le clr d le clr d le clr d le clr d le clr d le clr d le clr supertex inc. supertex inc. www .supertex.com
2 HV2901 doc.# dsfp-HV2901 b011713 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. parameter value v dd logic supply -0.5v to +6.5v v pp -v nn differential supply 220v v pp positive supply -0.5v to v nn +200v v nn negative supply +0.5v to -200v logic input voltage -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65c to 150c power dissipation 1.5w recommended operating conditions sym parameter value v dd logic power supply voltage 3.0v to 5.5v v pp positive high voltage supply +40v to v nn +200v v nn negative high voltage supply -40v to -160v v ih high level input voltage 0.9v dd to v dd v il low level input voltage 0v to 0.1v dd v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c pin confguration notes: 1. power up/down sequence is arbitrary except gnd must be powered-up frst and powered-down last. 2. v sig must be v nn v sig v pp or foating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. product marking 64-lead qfn (k6) 64-lead qfn (k6) (top view) package may or may not include the following marks: si or 1 64 l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packagin g HV2901k6 lllllllll yyww aaa ccc -g indicates package is rohs compliant (green) ordering information part number package option packing HV2901k6-g 64-lead qfn (9x9) 260/tray typical thermal resistance package ja 64-lead qfn 21 o c/w supertex inc. www .supertex.com
3 HV2901 doc.# dsfp-HV2901 b011713 dc electrical characteristics (over recommended operating conditions unless otherwise specifed ) sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max r ons small signal switch on-resistance - 30 - 26 38 - 48 i sig = 5.0ma v pp = +40v, v nn = -160v - 25 - 22 27 - 32 i sig = 200ma - 25 - 22 27 - 30 i sig = 5.0ma v pp = +100v, v nn = -100v - 18 - 18 24 - 27 i sig = 200ma - 23 - 20 25 - 30 i sig = 5.0ma v pp = +160v, v nn = -40v - 22 - 16 25 - 27 i sig = 200ma r ons small signal switch on-resistance matching - 20 - 5.0 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switch on-resistance - - - 15 - - - v sig = v pp -10v, i sig = 1a r int value of output bleed resistor - - 20 35 50 - - k output switch to r gnd i rint = 0.5ma i sol switch off-leakage per switch - 5.0 - 1.0 10 - 15 a v sig = v pp -10v, v nn +10v v os dc offset switch off - 300 - 100 300 - 300 mv no load dc offset switch on - 500 - 100 500 - 500 i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - i sw switch output peak current - 3.0 - 3.0 2.0 - 2.0 a v sig duty cycle < 0.1% f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp average v pp supply current - 16 - - 20 - 22 ma v pp = +40v, v nn = -160v all output switches are turning on and off at 50khz with no load - 14 - - 14 - 14 v pp = +100v, v nn = -100v - 14 - - 14 - 14 v pp = +160v, v nn = -40v i nn average v nn supply current - 16 - - 20 - 22 ma v pp = +40v, v nn = -160v all output switches are turning on and off at 50khz with no load - 14 - - 14 - 14 v pp = +100v, v nn = -100v - 14 - - 14 - 14 v pp = +160v, v nn = -40v i dd average v dd supply current - 8.0 - - 8.0 - 8.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq quiescent v dd supply current - 10 - - 10 - 10 a all logic inputs are static i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- * see test circuits on page 5 supertex inc. www .supertex.com
4 HV2901 doc.# dsfp-HV2901 b011713 ac electrical characteristics (over recommended operating conditions unless otherwise specifed) sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max t sd set up time before le rises 25 - 25 - - 25 - ns --- t wle time width of le 56 - - 56 - 56 - ns v dd = 3.0v 12 - - 12 - 12 - v dd = 5.0v t do clock delay time to data out 8.0 40 8.0 19 40 8.0 40 ns v dd = 3.0v 8.0 30 8.0 15 30 8.0 30 v dd = 5.0v t wclr time width of clr 55 - 55 - - 55 - ns --- t su set up time data to clock 21 - 21 - - 21 - ns v dd = 3.0v 7.0 - 7.0 - - 7.0 - v dd = 5.0v t h hold time data from clock 5.0 - 5.0 - - 5.0 - ns v dd = 3.0v 7.0 - 7.0 - - 7.0 - v dd = 5.0v f clk clock frequency - 8 - - 8 - 8 mhz v dd = 3.0v - 20 - - 20 - 20 v dd = 5.0v t r , t f clock rise and fall times - 50 - - 50 - 50 ns --- t on turn on time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k t off turn off time - 5.0 - - 5.0 - 5.0 dv/dt maximum v sig slew rate - 20 - - 20 - 20 v/ns v pp = +40v, v nn = -160v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +160v, v nn = -40v k o off isolation -30 - -30 -33 - -30 - db f = 5.0mhz, 1.0k//15pf load -58 - -58 -60 - -58 - f = 5.0mhz, 50 load k cr switch crosstalk -60 - -60 -70 - -60 - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd - 14 - 9.0 14 - 14 pf v sig = 0, f = 1.0mhz, both sw off off capacitance y to gnd - 28 - 18 28 - 28 c sg(on) on capacitance sw to gnd - 33 - 23 33 - 33 pf v sig = 0, f = 1.0mhz, one sw on, one sw off on capacitance y to gnd - 33 - 23 33 - 33 +v spk output voltage spike sw - - - - +150 - - mv v pp = +40v, v nn = -160v r load = 50 -v spk - - - - -150 - - +v spk - - - - +150 - - v pp = +100v, v nn = -100v r load = 50 -v spk - - - - -150 - - +v spk - - - - +150 - - v pp = +160v, v nn = -40v r load = 50 -v spk - - - - -150 - - * see test circuits on page 5 supertex inc. www .supertex.com
5 HV2901 doc.# dsfp-HV2901 b011713 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max +v spk output voltage spike y - - - - +150 - - mv v pp = +40v, v nn = -160v r load = 50 -v spk - - - - -150 - - +v spk - - - - +150 - - v pp = +100v, v nn = -100v r load = 50 -v spk - - - - -150 - - +v spk - - - - +150 - - v pp = +160v, v nn = -40v r load = 50 -v spk - - - - -150 - - qc charge injection (per switch) - - - 820 - - - pc v pp = +40v, v nn = -160v - - - 600 - - - v pp = +100v, v nn = -100v - - - 350 - - - v pp = +160v, v nn = -40v ac electrical characteristics (cont.) supertex inc. www .supertex.com
6 HV2901 doc.# dsfp-HV2901 b011713 test circuits rg nd rgnd rg nd rgnd rg nd rgnd rgnd nc 50 nc y23 v out nc nc rgnd sw 1 sw 0 y0 1 sw 1 sw 0 y0 1 sw 1 sw 0 y0 1 sw 1 sw 0 y0 1 sw 1 sw 0 y01 sw 1 sw 0 y01 sw 1 sw 0 y0 1 sw 1 sw 0 y01 v pp -10v switch off leakage dc offset on/off t on /t off te st circuit off isolation isolation diode current charge injection output v oltage spike sw v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd v pp vpp vdd 5.0v v nn vnn gnd output v oltage spike y k o = 20log v out v in v in = 10v p-p @5.0mhz r load 10k v out v out v out v out v out v out v out nc nc nc nc nc nc v pp -10v i sol v sig i id v nn nc nc nc q = 1000pf ? ?v out 50 50 r l 1k nc 1000p f +v spk -v spk +v spk -v spk r l 1k 50 50 crosstalk k cr = 20log v out v in y01 sw1 sw3 sw2 sw0 v pp vpp vdd 5.0v v nn vnn gnd v in = 10v p-p @5.0mhz v pp vpp vdd 5.0v v nn vnn gnd supertex inc. www .supertex.com
7 HV2901 doc.# dsfp-HV2901 b011713 logic timing waveforms truth table da ta in le cl oc k of f on v out (typ) 50 % 50% 50% 50% t wle t sd 50% 50% t su t h t off 50% t do t on t wcl cl r d n+1 d n d n-1 50 % 50 % 90% 10 % da ta out d0 d1 ... d15 d16 ... d31 le clr sw0 sw1 ... sw15 sw16 ... sw31 l - ... - - ... - l l off - ... - - ... - h - - - - l l on - - - - - l - - - l l - off - - - - h - - - l l - on - - - - - - - - l l - - - - - - - - - - l l - - - - - - - l - - l l - - off - - - - h - - l l - - on - - - - - l - l l - - - off - - - - h - l l - - - on - - - - - - l l - - - - - - - - - - l l - - - - - - - - - - l l - - - - - - - - - - l l - - - - - - - - - l l l - - - - off - - - - h l l - - - - on x x x x x x x h l hold previous state x x x x x x x x h all switches off notes: 1. the 32 switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. all 32 switches go to a state retaining their latched condition at the rising edge of le. when le is low the shift registers data fow through the latch. 4. d out is high when data in the register 31 is high. 5. shift registers clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs. supertex inc. www .supertex.com
8 HV2901 doc.# dsfp-HV2901 b011713 pin function 1 sw30 2 y3031 3 sw31 4 nc 5 clr 6 nc 7 le 8 clk 9 vdd 10 din 11 gnd 12 dout 13 nc 14 sw0 15 y01 16 sw1 pin function 17 sw2 18 y23 19 sw3 20 sw4 21 y45 22 sw5 23 sw6 24 y67 25 sw7 26 sw8 27 y89 28 sw9 29 sw10 30 y1011 31 sw11 32 sw12 pin function 33 y1213 34 sw13 35 vpp 36 rgnd 37 vnn 38 sw14 39 y1415 40 sw15 41 sw16 42 y1617 43 sw17 44 vnn 45 rgnd 46 vpp 47 sw18 48 y1819 pin function 49 sw19 50 sw20 51 y2021 52 sw21 53 sw22 54 y2223 55 sw23 56 sw24 57 y2425 58 sw25 59 sw26 60 y2627 61 sw27 62 sw28 63 y2829 64 sw29 pin function vsub (thermal pad) the central thermal pad on the bottom of package must be connected to vnn externally supertex inc. www .supertex.com
9 HV2901 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-HV2901 b011713 64-lead qfn package outline (k6) 9.00x9.00mm body, 1.00mm height (max), 0.50mm pitch seating plane t op vi ew side v iew bottom v iew d e d2 v iew b vi ew b 1 note 3 note 2 64 1 64 e2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) e b l l1 a a1 a3 symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.20 8.90 7.60 8.90 7.60 0.50 bsc 0.30 0.00 0 o nom 0.90 0.02 0.25 9.00 7.70 9.00 7.70 0.40 - - max 1.00 0.05 0.30 9.10 7.80 9.10 7.80 0.50 0.15 14 o drawings are not to scale. supertex doc.#: dspd-64qfnk69x9p050, version b020112 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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